One of the present challenges for SMPC's is achieving good load transient response. When the load current increases steeply and drastically, the switch mode power converter must compensate for the lack of the output current as quickly as possible to avoid undershoot of the output voltage of the SMPC. A solution known in the art is transient detector or “panic” comparator within the switch mode power converter for determining that a load transient has occurred. If the transient detector determines that there is an excess output voltage drop at the output of the SMPC, the switching section is activated such that current is allowed to flow into an inductor of the filter section of the SMPC.
FIG. 1 is a schematic of a buck SMPC of the prior art. Referring to FIG. 1, the buck SMPC has a control stage 5, a switch stage 10, filter stage 15. The control stage 5 provides the necessary signals for activating and deactivating the switch stage 10 to control the current ILX applied to the filter stage 15. The control stage 5 has an error amplifier 20 that receives a feedback voltage VFB indicative of the output voltage VOUT from the output terminal 55 of the buck SMPC. A target reference voltage source 35 provides a target reference voltage VREF to a second input of the error amplifier 20. The difference between the feedback voltage VFB and the target reference voltage VREF is used to generate an error signal VERR indicative of a difference between the output voltage VOUT of the SMPC and the target reference voltage VREF. The target reference voltage VREF is a design voltage level for the output voltage VOUT of the SMPC and thus the control stage 5 is structured to minimize the error signal VERR.
The output of the error amplifier 20 is connected to the input of the pulse width modulation (PWM) generator section 25. The PWM generator section 25 includes a PWM comparator 27 and a ramp generator 29. The PWM comparator 27 receives the error signal VERR at a noninverting input and a ramp clocking signal as created by the ramp generator 29 at the inverting input. The PWM comparator 27 compares the error signal VERR and the ramp clocking signal and generates a digital PWM signal VPWM at the output of the PWM comparator 27. When error signal VERR applied to the noninverting (+) input of the comparator is less than the ramp clocking signal applied to the inverting (−) input, the digital PWM signal VPWM will be logical (0). As soon as the ramp clocking signal becomes larger than the error signal VERR, the digital PWM signal VPWM will be logical (1). The ramp clocking signal generates the digital PWM signal VPWM that has a pulse width proportional to Vout at equilibrium condition and is based the error signal VERR. If there is a very light load current ILOAD, the duty cycle of the digital PWM signal VPWM is relatively small.
If a load transient causes a significant increase in the load current ILOAD, the digital PWM signal VPWM must increase its duty cycle very quickly. To assist in this a panic comparator 40 is added to the control stage 5. The panic comparator 40 is connected to a negative terminal of the undershoot threshold voltage source 45. The positive terminal of the undershoot threshold voltage source 45 is connected to the positive terminal of the target reference voltage source 35. The combination of the undershoot voltage source 45 and the target reference voltage source 35 sets the undershoot threshold voltage level VTHUS at the noninverting terminal (+) of the panic comparator 40 at a voltage level of the target reference voltage VREF less the undershoot threshold voltage level VTHUS generated by the undershoot voltage source 45.
The inverting terminal (−) of the panic comparator 40 receives the feedback voltage VFB for comparison with the undershoot threshold voltage level VTHUS. The panic voltage VPANIC of the panic comparator 40 is activated to a logical (1) when the feedback voltage VFB is less than the undershoot threshold voltage level VTHUS.
The pulse width modulation output PWM of the VPWM comparator 27 and the panic voltage VPANIC of the panic comparator 40 are applied to logical OR circuit 30. The output of the logical OR circuit 30 is the input to the driver circuit 50. The driver circuit 50 conditions the output signal of the logical OR circuit 30 for driving the gates of the PMOS transistor P1 and the NMOS transistor N1. The source of the PMOS transistor P1 is connected to the input voltage VIN of the buck SMPC. The source of the NMOS transistor N1 is connected to the ground reference voltage source. The drains of the PMOS transistor P1 and the NMOS transistor N1 are connected to the input of the filter circuit 15 and thus to a first terminal of an inductor LX. The activation and deactivation of the PMOS transistor P1 and the NMOS transistor N1 determines the direction of the output current ILX of the switch stage 10 which determines the output voltage level VAX of the switch circuit 10. The inductor LX and the load filter capacitor CL filter the high frequency signals and noise from the output voltage VLX to generate the output voltage VOUT of the buck SMPC at the output terminal 55.
FIG. 2 is a plot of the voltage and current waveforms developed within the buck SMPC of the prior art of FIG. 1. When the load current ILOAD increases precipitously at the time τ1, the output voltage VOUT begins to fall since the duty cycle of the output of the driver circuit 50 is not large enough to support the level of the load current ILOAD. When the output voltage VOUT has decreased to the undershoot threshold voltage level VTHUS at the time τ2, the panic comparator 40 is activated and the panic voltage VPANIC rises to the voltage level of the logical (1). The logical (1) voltage level of the panic voltage VPANIC is transferred through the logical OR circuit 30 and the driver circuit 50 to turn on the PMOS transistor P1. The voltage VLX at the junction of the drains of the PMOS transistor P1 and the NMOS transistor N1 rises at the time τ2. This causes the current ILX through the inductor LX to increase. At the time τ3, the inductor current ILX is equal to the load current ILOAD and the slope of the output voltage VOUT changes from negative (decreasing voltage) to positive (increasing voltage). The panic voltage VPANIC remains at the logical (1) level, since the output voltage VOUT remains less than the undershoot threshold voltage level VTHUS and thus the PMOS transistor P1 remains turned on and conducting the current ILX into the inductor LX. At the time τ4, the output voltage VOUT increases to pass the undershoot threshold voltage level VTHUS and the panic comparator 40 is deactivated to cause the panic voltage VPANIC to fall to the voltage level of the logical (0). The logical (0) voltage level of the panic voltage VPANIC is transferred through the logical OR circuit 30 and the driver circuit 50 to turn off the PMOS transistor P1. Because of the timing of the ramp clocking signal from the ramp generator 29, the PMOS transistor P1 remains turned on past the time τ4 thus permitting the inductor current ILX to continue to rise until the end of the cycle of the ramp clocking signal at the time τ5. At the time τ6, the output voltage VOUT passes the target reference voltage level VREF and begins to overshoot the desired output voltage VOUT. The excessive inductor current ILX causes the output voltage VOUT of the buck SMPC to have a large overshoot between the time τ6 and the time τ7 when the pulse width modulation generator 25 regains control. The large overshoot of the output voltage VOUT caused by the excessive inductor current ILX is undesirable impacting the performance of the electronic load circuit 60.